| United States Patent Office | 3,356,858 Patented Dec. 5, 1967 |
3,356,858
LOW STAND-BY POWER COMPLEMENTARY FIELD EFFECT CIRCUITRY
Filed June 18 1963, Ser. No. 288,786
3 Claims. (307-88.5)
ABSTRACT OF THE DISCLOSURE
A combinatorial switching circuit using a pair of complementary insulated field-effect transistors, each having one of its source or drain electrodes connected to the source or drain electrode of the other; a signal of a single predetermined, single polarity voltage is applied to both gates of both devices to obtain the necessary switching operation.
The present invention relates in general to transistor circuits, and more particularly to a circuit employing field-effect semiconductor devices.
Heretofore, logic networks or circuits required passive load elements, such as a resistor or some other passive load component. By employing a passive load element, such as a load resistor, in the logic circuit, power was dissipated during the standby period or during the time intervals in which no switching operation was occurring.
Accordingly, an object of the present invention is to provide circuits in which power losses are minimized.
Another object of the present invention is to provide logic circuits in which power dissipation is reduced during stand-by periods.
Another object of the present invention is to provide a transistor circuit employing field-effect semiconductor devices wherein a field-effect semiconductor device of one carrier type is used as the active load for the field-effect semiconductor device of the opposite carrier type.
Another object of the present invention is to provide a transistor circuit in which an inverter action is produced without employing any passive load element.
Another object of the present invention is to provide a transistor circuit in which a switching action is created at a faster rate while reducing the stand-by power normally consumed by the passive load resistance.
Another object of the present invention is to provide improved integrated microcircuits.
Another object of the present invention is to provide switching circuits wherein leakage current is reduced.
Another object of the present invention is to provide logic circuits adapted for improved fan out.
Another object of the present invention is to provide logic circuits with improved tolerance for high temperature differentials between different circuit elements.
Another object of the present invention is to provide integrated logic circuits adapted for efficient cooling with a reduced amount of heat exchange area.
Another object of the present invention is to provide micrologic circuits with a low stand-by power density and a high switching power density, whereby a high packing density is obtained.
Other and further objects and advantages of the present invention will be apparent to one skilled in the art from the following description taken in conjunction with the accompanying drawings, in which:
FIG. 1 is an enlarged schematic perspective view of an N-type insulated gate field-effect semiconductor device employed in the present invention.
FIG. 1A is a vertical sectional view of the N-type insulated gate field-effect semiconductor device taken along line 1A—1A of FIG. 1.
FIG. 2 is an enlarged schematic perspective view of a P-type insulated gate field-effect semiconductor device employed in the present invention.
FIG. 2A is a vertical sectional view of the P-type insulated gate field-effect semiconductor device taken along line 2A—2A of FIG. 2.
FIG. 3 is a schematic circuit diagram of the N-type insulated gate field-effect semiconductor device shown in FIG. 1 with the biasing potential applied thereto.
FIG. 4 is a schematic circuit diagram of the P-type insulated gate field-effect semiconductor device shown in FIG. 2 with the biasing potential applied thereto.
FIG. 5 is a schematic diagram of an inverter circuit employing the insulated gate field-effect semiconductor devices illustrated in FIGS. 1 and 2.
FIGS. 5A and 5B are graphs illustrating input-output characteristics for the inverter circuit shown in FIG. 5.
FIG. 6 is a schematic diagram of a NAND logic circuit using the insulated gate field-effect semiconductor devices shown in FIGS. 1 and 2.
FIG. 7 is a schematic diagram of a NOR logic circuit employing the insulated gate field-effect semiconductor devices shown in FIGS. 1 and 2.
FIG. 8 is an enlarged schematic cross sectional view of the insulated field-effect semiconductor device shown in FIGS. 1 and 2 integrated into a single semiconductor chip or slice.
FIG. 9 is a graph illustrating the drain current as a function of the gate voltage for a typical device shown in FIGS. 1 and 1A.
FIG. 10 is a graph illustrating the drain current as a function of the gate voltage for a typical device shown in FIGS. 2 and 2A.
Illustrated in FIGS. 1 and 1A is an N-type external insulated gate field-effect semiconductor device 10 employed in the present invention, which comprises a substrate or body 11 of semiconductor material, such as silicon. The silicon body 11 is doped in a conventional manner with P-type impurities, such as aluminum, gallium, boron or indium. Also formed in the silicon body or wafer 11 are N-type-diffused regions 12 and 13, which extend to an upper surface 14 of the P-type silicon wafer 11. The N-type diffused regions 12 and 13 are formed in a conventional manner by diffusing antimony, arsenic or phosphorus into the silicon body 11.
An insulated layer 22 preferably of silicon dioxide is thermally grown on the surface 14 of the silicon body 11 and is located in part between the drain contact 20 and the source contact 21. The drain contact 20 and the source contact 21 are formed by evaporation of a suitable metallic substance, such as aluminum; a metallic gate 25 of preferably aluminum is disposed in contact with the portion of the insulated layer 22 located between the drain contact 20 and the source contact 21, such that the metal overlaps the inside edges of diffused regions 12 and 13. Lead 20' is attached to the drain contact 20 and a lead 25' is attached to the gate 25. The source electrode 21 has a lead 21' attached thereto and connected to the substrate 11.
In FIGS. 2 and 2A is illustrated a P-type externally insulated gate field-effect semiconductor device 30 which
