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tively, through conductors 53–55. An output signal Vo is taken from the drains 20 and 36 of the semiconductor devices 10 and 30, respectively, over conductors 56, 52 and 51.
When the input signal Vi which is impressed on the gates 25 and 41, is greater than the positive critical potential, the P-type field-effect semiconductor device 30 will not conduct and the N-type field-effect semiconductor device 10 will conduct making the output voltage Vo negative. See FIGS. 5A and 5B to show the output voltage Vo for a slowly charging input signal and for a rapidly rising pulse. When the input signal Vi, which is impressed on the gates 25 and 41, is more negative than the negative critical potential, the N-type field-effect semiconductor device 10 will not conduct and the P-type field-effect semiconductor device 30 will conduct making the output voltage Vo positive.
Accordingly, the circuit 50 produces a switching or inverting action without employing any passive load component, such as a load resistor. Further, it is to be observed from the inverter circuit 50 that only one of the semiconductor devices 10 and 30 will conduct if the input voltage Vi is above a predetermined positive value or below a predetermined negative value. Therefore, if the total supply voltage difference 2V is great enough so that when Vi goes from -V to +V, device 10 will turn on and device 30 will turn off, then power is dissipated only during the switching operation and not during any stand-by condition. Hence, a low-power system is achieved. In actual practice the power consumed during a stand-by operation is less than 10 nanowatts per node and, yet, the inverter circuit 50 can effect switching in less than 20 nanoseconds. Moreover, the conducting field-effect semiconductor device will be turned on to a low resistance state, while the the non-conducting field-effect semiconductor device is turned off to an extremely high resistance state, so that output circuit capacities can be rapidly charged during switching. From the foregoing, it is to be observed that the usual requirement of more stand-by power for rapid switching is avoided, since stand-by power is not dissipated in any passive load resistor or component.
In FIG. 6 is illustrated a NAND logic or gate circuit 60 employing the complementary N and P-type insulated field-effect semiconductor devices 10 and 30. A plurality of P-type insulated field-effect semiconductor devices, such as 30a, 30b and 30c, are connected in parallel. Impressed on the source electrodes 37a, 37b and 37c of the semiconductor devices 30a-30c, respectively, is a biasing potential +V. The output of the logic circuit is taken at the drain electrodes 36a-30c of the semiconductor devices 30a-30c, respectively.
Connected in series with the parallel P-type insulated field-effect semiconductor devices 30a-30c are N-type insulated field-effect semiconductor devices 10a-10c. Applied to the source contact 21c of the semiconductor device 10c is a biasing potential -V. The P-type field-effect semiconductor device 30a and the N-type field effect semiconductor device 10a are complementary. Further, the P-type field-effect semiconductor device 30b and the N-type field-effect semiconductor device 10b are complementary. Similarly, the P-type field-effect semiconductor device 30c and the N-type field-effect semiconductor device 10c are complementary.
In the operation of the NAND logic circuit 60, an input signal of +V or -V is impressed on the gates 25a and 41a of the complementary semiconductor devices 10a and 30a. In a similar manner, an input signal is fed to the gates 25b and 41b of the complementary semiconductor devices 10b and 30b. Likewise, an input signal C is transmitted to the gates of the complementary semiconductor devices 10c and 30c. The input signals A, B and C are transmitted simultaneously to the field-effect semiconductor devices in the manner above indicated.
Should all signals A, B and C be at +V so that their associated P-type field-effect semiconductor devices are not conductive and their associated N-type devices are conductive, then there will be a negative output voltage at Y. When the semiconductor devices 30a-30c conduct, the complementary semiconductor devices 10a-10c, respectively, provide a high impedance and the active load.
A NOR logic or gate circuit 70. is shown in FIG. 7, which employs the complementary N and P type insulated field-effect semiconductor devices 10 and 30. A plurality of N-type insulated field-effect semiconductor devices, such as 10d-10f are connected in parallel. Impressed on the source electrodes 21d-21f of the semiconductor devices 10d-10f is a biasing potential -V. Connected in series with the semiconductor devices 10d-10f are parallel connected P-type insulated field-effect semiconductor devices 30d-30f. Applied to the source electrode 37f of the semiconductor device 30f is a biasing potential V'. The output of the logic circuit 70 is taken at Y' at the drain electrodes 20d-20f of the semiconductor devices 10d-10f.
The N-type field-effect semiconductor device 10d and the P-type field-effect semiconductor device 30d are complementary. Likewise, the N-type field-effect semiconductor device 10e and the P-type field-effect semiconductor device 30e are complementary. Similarly, the N-type field-effect semiconductor device 10f and the P-type field-effect semiconductor device 30f are complementary.
In the operation of the NOR logic circuit 70, an input signal D is transmitted to the gates 25d and 41d of the complementary semiconductor devices 10d and 30d. Likewise, an input signal E is fed to the gates 25e and 41e of the complementary semiconductor devices 10e and 30e. In a similar manner, an input signal F is impressed on the gates 25f and 41f of the complementary semiconductor devices 10f and 30f.
If any one or more of the input signals D, E and F is equal to +V, then the associated P-type field-effect semiconductor device or devices 30d-30f will not conduct and its or their complementary N-type field-effect semiconductor devices 10d-10f will conduct. As a result thereof, a negative potential will appear at the terminal Y'. The non-conducting field-effect semiconductor device or devices 10d-10f provide a high impedance and also provide the active load, respectively, for the complementary conducting field-effect semiconductor devices 30d-30f. Hence, if any one or more of the P-type semiconductor devices 30d-30 f conducts, a positive output signal is produced at terminal Y'.
Illustrated in FIG. 8 is a semiconductor unitary structure 80, which comprises a plurality of semiconductor devices, such as N-type external insulated gate field-effect semiconductor device 81 and a complementary P-type insulated gate field-effect semiconductor device 82, which are integrally formed on a single chip or slice 83.
In the preferred embodiment the chip or body 83 is of silicon and is doped in a conventional manner with N-type impurities, such as antimony, arsenic or phosphorous. For producing the P-type field-effect semiconductor device 82, P-type diffused regions 84 and 85 are formed in the N-type silicon body 83 and extend to an upper surface 86 of the silicon chip 83. Th P-type diffused regions 84 and 85 are formed in a conventional manner by diffusing a P-type impurity such as aluminium, boron or indium into the silicon body 83.
For producing the N-type field-effect semiconductor device 81, the silicon body 83 is doped in a conventional manner with P-type impurities, such as aluminum, boron or indium to form a P-type region 90 within the N-type silicon body 83. Formed in the P-type region are N-type diffused regions 91 and 92, which extend to the upper surface 86 of the silicon body 83.
The N-type diffused regions 91 and 92 are formed in a conventional manner by diffusing antimony, arsenic or phosphorous into the P-type region 90. An insulated layer 95 preferably of silicon dioxide is thermally grown
